1. Field of the Invention
This invention relates to a semiconductor memory device and a method of fabricating the same. More particularly, the invention relates to a memory device with cell transistors formed on a SOI substrate, each cell transistor having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body.
2. Description of Related Art
Recently, for the purpose of alternative use or replacement of conventional DRAMs, a semiconductor memory device that has a more simplified cell structure for enabling achievement of dynamic storability has been provided. A memory cell (i.e., cell transistor) is formed of a single transistor which has an electrically floating body (channel body) as formed on a silicon-on-insulator (SOI) substrate. This cell transistor stores two-value data as follows: a first data (for example, logic “1” data) is stored as a state that an excess number of majority carriers are accumulated or stored in the body; and a second data (for example, logic “0” data) is stored as a state that the excessive majority carriers are drawn out from the body. Such the memory has been described in, for example, Unexamined Japanese Patent Application Publication No. 2003-68877.
The memory cell of the type stated above will be referred to hereinafter as a “floating-body cell (FBC)”. A semiconductor memory using FBCs will be referred to as a “FBC memory”. The FBC memory makes use of no capacitors unlike currently available standard DRAM chips so that the memory cell is simpler in memory cell array structure and smaller in unit cell area than ever before. Thus, the FBC memory is readily scalable in cell structure and advantageously offers much enhanced on-chip integration capabilities.
For writing logic “1” data in the FBC memory, impact ionization near the drain of a memory cell is utilized. More specifically, with giving an appropriate bias condition for permitting flow of a significant channel current in the memory cell, majority carriers (holes in case of n-channel cell transistor) are generated by impact ionization and stored in the floating body. Writing logic “0” data is performed by setting a PN junction between the drain and the body in a forward bias state, thereby releasing the body's majority carries toward the drain side.
A difference between carrier storage states of the floating body appears as a difference between threshold voltages of the cell transistor. Thus, detect whether an appreciable cell current is present or absent, alternatively, whether the cell current is large or small in magnitude, by applying a read voltage to the gate of the cell transistor, and it is possible to determine or sense whether the resultant read data is a logic “0” or “1”. The carrier accumulation state of the body may be retained with applying a certain holding voltage to the gate.
To achieve highly integrated FBC memories, it is desirable to use such an arrangement that adjacent two cell transistors arranged in the direction of the bit line share a source/drain layer without disposing a device isolation area between them. One problem with this, however, is that data reliability is reduced.
The problem will be explained in detail with reference to FIG. 16. FIG. 16 shows two cell transistors MTi and MTi+1 which are disposed as adjacent in the direction of a bit line (BL). Each cell transistor is formed on a p-type silicon layer 3 serving as a channel body. The silicon layer 3 is formed on a silicon substrate 1 with an insulating film 2 interposed therebetween. Gate electrodes 4 of the cell transistors MTi and MTi+1 are formed as elongated in the direction perpendicular to the drawing plain to constitute word lines WLi and WLi+1, respectively.
The two cell transistors MTi and MTi+1 share an n-type diffusion layer (i.e., drain layer) 5, to which the bit line BL is contacted. Other n-type layers (i.e., source layers) of these transistors are shared by these cell transistors and adjacent ones (not shown), to which source lines are contacted.
FIG. 16 shows carrier movement in the channel body in a state where “0” write is performed in one cell transistor MTi within two cell transistors MTi and MTi+1. In this case, with applying a forward bias between the drain diffusion layer 5 connected to the bit line BL and the channel body 3, holes (i.e., majority carriers designated by symbol “+”) in the channel body 3 of the cell transistor MTi are drawn to the drain layer 5.
At this time, part of the holes drawn in the drain diffusion layer 5 passes through this layer 5 to be injected into the channel body of the adjacent cell transistor MTi1+1. This is a result of that a parasitic pnp transistor formed between two channel bodies of the cell transistors MTi and MTi+1 becomes on. Therefore, if the cell transistor MTi+1 is storing “0” data, “1” may be erroneously written into it. This erroneous write (i.e., data destruction) will be referred to as “bipolar disturbance” because it is due to a parasitic bipolar transistor.
As described above, the conventional FBC memory has a problem that approach for achieving high integration density leads to bipolar disturbance, i.e., reduction of data reliability due to interference between adjacent cell transistors. If adjacent two cell transistors are perfectly isolated from each other, the bipolar disturbance will be solved. However, this ruins the feature of the FBC memory that it may be integrated with a high density. Therefore, it is required to reduce the bipolar disturbance of cell transistors without ruining the feature of the FBC memory, and without reducing the characteristics of logic transistors in peripheral circuitry.